**Recent Articles in Conference Proceedings**

**Book Chapters and Technical Reports**

**Journals**

- [J36] J. Zhu, W. Tang, C.-E. Lee, H. Ye, E. McCreath, and Z. Zhang, “VOTA: A heterogeneous multicore visual object tracking accelerator using correlation filters,”
*IEEE J. Solid-State Circuits*(Early Access). - [J35] X. Wang, R. Pinkham, M. A. Zidan, F.-H. Meng, M. P. Flynn, Z. Zhang, and W. D. Lu, “TAICHI: A tiled architecture for in-memory computing and heterogeneous integration,”
*IEEE Trans. Circuits Syst. II, Exp. Briefs*, vol. 69, no. 2, pp. 559-563, Feb. 2022. - [J34] R. Pinkham, A. Berkovich, and Z. Zhang, “Near-sensor distributed DNN processing for augmented and virtual reality,”
*IEEE J. Emerging Sel. Topics in Circuits Syst.*, vol. 11, no. 4, pp. 663-676, Dec. 2021. - [J33] W. Tang, C.-H. Chen, and Z. Zhang, “A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM message-passing detector for a 128×32 massive MIMO uplink system,”
*IEEE J. Solid-State Circuits*, vol. 56, no. 6, pp. 1722-1731, Jun. 2021. - [J32] J.-F. Zhang, C.-E. Lee, C. Liu, Y. S. Shao, S. W. Keckler, and Z. Zhang, “SNAP: An efficient sparse neural acceleration processor for unstructured sparse deep neural network inference,”
*IEEE J. Solid-State Circuits*, vol. 56, no. 2, pp. 636-647, Feb. 2021. - [J31] Y. Tao, S.-G. Cho, and Z. Zhang, “A configurable successive-cancellation list polar decoder using split-tree architecture,”
*IEEE J. Solid-State Circuits*, vol. 56, no. 2, pp. 612-623, Feb. 2021. - [J30] J. M. Correll, V. Bothra, F. Cai, Y. Lim, S. H. Lee, S. Lee, W. D. Lu. Z. Zhang, and M. P. Flynn, “A fully-integrated reprogrammable CMOS-RRAM compute-in-memory coprocessor for neuromorphic applications,”
*IEEE J. Exploratory Solid-State Computational Devices and Circuits*, vol. 6, no. 1, pp. 36-44, Jun. 2020. - [J29] T. Chen, J. Botimer, T. Chou, and Z. Zhang, “A 1.87mm2 56.9GOPS accelerator for solving partial differential equations,”
*IEEE J. Solid-State Circuits*, vol. 55, no. 6, pp. 1709-1718, Jun. 2020. - [J28] Y. Tao, S. Sun, and Z. Zhang, “Efficient post-processors for improving error-correcting performance of LDPC codes,”
*IEEE Trans. Circuits Syst. I, Reg. Papers*, vol. 66, no. 10, pp. 4032-4043, Oct. 2019. - [J27] F. Cai, J. M. Correll, S. H. Lee, Y. Lim, V. Bothra, Z. Zhang, M. P. Flynn, W. D. Lu, “A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations,”
*Nature Electronics*, vol. 2, no. 7, pp. 290-299, Jul. 2019. - [J26] T. Chen, C.-E. Lee, C. Liu, and Z. Zhang, “A 135mW 1.70TOPS sparse video sequence inference SoC for action classification,”
*IEEE J. Solid-State Circuits*, vol. 54, no. 7, pp. 2081-2090, Jul. 2019. - [J25] W. Tang, C.-H. Chen, and Z. Zhang, “A 2.4mm2 130mW MMSE-nonbinary LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS,”
*IEEE J. Solid-State Circuits*, vol. 54, no. 7, pp. 2070-2080, Jul. 2019. - [J24] C. Liu, S.-G. Cho, and Z. Zhang, “A 2.56-mm2 718GOPS configurable spiking convolutional sparse coding accelerator in 40-nm CMOS,”
*IEEE J. Solid-State Circuits*, vol. 53, no. 10, pp. 2818-2827, Oct. 2018. - [J23] M. Zidan, Y. Jeong, J. H. Shin, C. Du, Z. Zhang, and W. Lu, “Field-programmable crossbar array (FPCA) for reconfigurable computing,”
*IEEE Trans. Multi-Scale Computing Syst.*, vol. 4, no. 4, pp. 698-710, Oct.-Dec. 2018. - [J22] S. Song, K. D. Choo, T. Chen, S. Jang, M. P. Flynn, and Z. Zhang, “A maximum-likelihood sequence detection powered ADC-based serial link,”
*IEEE Trans. Circuits Syst. I, Reg. Papers*, vol. 65, no. 7, pp. 2269-2278, Jul. 2018. - [J21] Z. Li, Q. Dong, M. Saligane, B. Kempke, L. Gong, Z. Zhang, R. Dreslinski, D. Sylvester, D. Blaauw, and H.-S. Kim, “A 1920 x 1080 30-frames/s 2.3 TOPS/W stereo-depth processor for energy-efficient autonomous navigation of micro aerial vehicles,”
*IEEE J. Solid-State Circuits.*, vol. 53, no. 1, pp. 76-90, Jan. 2018. - [J20] S. Sun and Z. Zhang, “Designing practical polar codes using simulation-based bit selection,”
*IEEE J. Emerging Sel. Topic Circuits Syst.*, vol. 7, no. 4, pp. 594-603, Dec. 2017. - [J19] P. M. Sheridan, F. Cai, C. Du, W. Ma, Z. Zhang, and W. D. Lu, “Sparse coding with memristor networks,”
*Nature Nanotechnology*, vol. 12, no. 8, pp. 784-789, May 2017. - [J18] J. Bell, P. Knag, S. Sun, Y. Lim, T. Chen, J. Fredenburg, C.-H. Chen, C. Zhai, A. Rocca, N. Collins, A. Tamez, J. Pernillo, J. Correll, Z. Zhang, and M. P. Flynn, “A 1.5GHz 6.144Tcorrelations/s 64×64 cross-correlator with 128 integrated ADCs for real-time synthetic aperture imaging,”
*IEEE J. Solid-State Circuits*, vol. 52, no. 5, pp. 1450-1457, May 2017. - [J17] F. Sheikh, C.-H. Chen, D. Yoon, B. Alexandrov, K. Bowman, A. Chun, H. Alavi, and Z. Zhang, “3.2 Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication,”
*J. Signal Process. Syst.*, vol. 84, no. 3, pp. 295-307, Jan. 2016. - [J16] C.-H. Chen, S. Song, and Z. Zhang, “An FPGA-based transient error simulator for resilient circuit and system design and evaluation,”
*IEEE Trans. Circuits Syst. II, Exp. Briefs*, vol. 62, no. 5, pp. 471-475, May 2015. - [J15] P. Knag, J. K. Kim, T. Chen, and Z. Zhang, “A sparse coding neural network ASIC with on-chip learning for feature extraction and encoding,”
*IEEE J. Solid-State Circuits*, vol. 50, no. 4, pp. 1070-1079, Apr. 2015. - [J14] Y. S. Park, Y. Tao, and Z. Zhang, “A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating,”
*IEEE J. Solid-State Circuits*, vol. 50, no. 2, pp. 464-475, Feb. 2015. - [J13] Y.-P. Chen, D. Jeon, Y. Lee, Y. Kim, Z. Foo, I. Lee, N. Langhals, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, “An injectable 64nW ECG mixed-signal SoC in 65nm for arrhythmia monitoring,”
*IEEE J. Solid-State Circuits*, vol. 50, no. 1, pp. 375-390, Jan. 2015. - [J12] C.-H. Chen, P. Knag, and Z. Zhang, “Characterization of heavy-ion-induced single-event effects in 65 nm bulk CMOS ASIC test chips,”
*IEEE Trans. Nucl. Sci.*, vol. 61, no. 5, pp. 2694-2701, Oct. 2014. - [J11] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, “Efficient hardware architecture for sparse coding,”
*IEEE Trans. Signal Process.*, vol. 62, no. 16, pp. 4173-4186, Aug. 2014. - [J10] C.-H. Chen, D. Blaauw, D. Sylvester, and Z. Zhang, “Design and evaluation of confidence-driven error-resilient systems,”
*IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 22, no. 8, pp. 1727-1737, Aug. 2014. - [J9] D. Jeon, M. Henry, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, “An energy efficient full-frame feature extraction accelerator with shift-latch FIFO in 28nm CMOS,”
*IEEE J. Solid-State Circuits*, vol. 49, no. 5, pp. 1247-1284, May 2014. - [J8] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, “Low-power high-throughput LDPC decoder using non-refresh embedded DRAM,”
*IEEE J. Solid-State Circuits*, vol. 49, no. 3, pp. 783-794, Mar. 2014. - [J7] P. Knag, W. Lu, and Z. Zhang, “A native stochastic computing architecture enabled by memristors,”
*IEEE Trans. Nanotechnol.*, vol. 13, no. 2, pp. 283-293, Mar. 2014. - [J6] D. Jeon, M. Seok, Z. Zhang, D. Blaauw, and D. Sylvester, “Design methodology for voltage-overscaled ultra-low-power systems,”
*IEEE Trans. Circuits Syst. II, Exp. Briefs*, vol. 59, no. 12, pp. 952-956, Dec. 2012. - [J5] J. K. Kim, J. A. Fessler, and Z. Zhang, “Forward-projection architecture for fast iterative image reconstruction in X-ray CT,”
*IEEE Trans. Signal Process.*, vol. 60, no. 10, pp. 5508-5518, Oct. 2012. - [J4] Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, “An efficient 10GBASE-T Ethernet LDPC decoder design with low error floors,”
*IEEE J. Solid-State Circuits*, vol. 45, no. 4, pp. 843-855, Apr. 2010. - [J3] L. Dolecek, Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, “Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes,”
*IEEE Trans. Inf. Theory*, vol. 56, no. 1, pp. 181-201, Jan. 2010. - [J2] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, “Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices,”
*IEEE Trans. Commun.*, vol. 57, no. 11, pp. 3258-3268, Nov. 2009. - [J1] L. Dolecek, P. Lee, Z. Zhang, V. Anantharam, B. Nikolic, and M. Wainwright, “Predicting error floors of LDPC codes: deterministic bounds and estimates,”
*IEEE J. Sel. Areas Commun.*, vol. 27, no. 6, pp. 908-917, Aug. 2009.

**Recent Conference Proceedings (2020- )**

- [C68] J. Correll, L. Jie, S. Song, S. Lee, J. Zhu, W. Tang, L. Wormald, J. Erhardt, N. Breil, R. Quon, D. Kamalanathan, S. Krishan, M. Chudzik, Z. Zhang, W. Lu, M. Flynn, “An 8-bit 20.7 TOPS/W multi-level cell ReRAM-based compute engine,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2022. - [C67] T. Chou, W. Tang, M. Rotaru, C. Liu, R. Dutta, S. Lim, D. Ho, S. Bhattacharya, and Z. Zhang, “NetFlex: A 22nm multi-chiplet perception accelerator in high-density fan-out wafer-level packaging,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2022. - [C66] Y. Tao and Z. Zhang, “DNC-aided SCL-flip decoding of polar codes,” in
*IEEE Global Commun. Conf.*(*GLOBECOM*), Dec. 2021. (**Best Paper Award**) - [C65] J.-F. Zhang and Z. Zhang, “Point-X: A spatial-locality-aware architecture for energy-efficient graph-based point-cloud deep learning,” in
*IEEE/ACM Int. Symp. Microarchitecture*(*MICRO*), Oct. 2021. - [C64] Y. Tao and Z. Zhang, “HiMA: A fast and scalable history-based memory access engine for differentiable neural computer,” in
*IEEE/ACM Int. Symp. Microarchitecture*(*MICRO*), Oct. 2021. - [C63] J.-F. Zhang and Z. Zhang, “Exploration of energy-efficient architecture for graph-based point-cloud deep learning,” in
*IEEE Workshop Signal Process. Syst.*(*SIPS*), Oct. 2021 (Invited). - [C62] S.-G. Cho, W. Tang, C. Liu, and Z. Zhang, “PETRA: A 22nm 6.97TFLOPS/W AIB-enabled configurable matrix and convolution accelerator integrated with an Intel Stratix 10 FPGA,” in
*Symp. VLSI Circuits*, Jun. 2021. - [C61] J. Zhu, W. Tang, C.-E. Lee, H. Ye, E. McCreath, and Z. Zhang, “VOTA: A 2.45TFLOPS/W heterogeneous multi-core visual object tracking accelerator based on correlation filters,” in
*Symp. VLSI Circuits*, Jun. 2021. - [C60] M. Rotaru, W. Tang, R. Dutta, and Z. Zhang, “Design and development of high density fan-out wafer level package (HD-FOWLP) for deep neural network (DNN) chiplet accelerators using advanced interface bus (AIB),” in
*IEEE Electronic Components and Technology Conf.*(*ECTC*), Jun. 2021. - [C59] C. Liu, J. Botimer, and Z. Zhang, “A 256Gb/s/mm-shoreline AIB-compatible 16nm FinFET CMOS chiplet for 2.5D integration with Stratix 10 FPGA on EMIB and tiling on silicon interposer,” in
*IEEE Custom Integrated Circuits Conf.*(*CICC*), Apr. 2021. (**Best Student Paper Candidate**) - [C58] R. Pinkham, S. Zeng, and Z. Zhang, “QuickNN: Memory and performance optimization of k-d tree based nearest neighbor search for 3D point clouds,” in
*IEEE Int. Symp. High-Performance Computer Architecture*(*HPCA*), San Diego, CA, Feb. 2020.

**Conference Proceedings (2010-2019)**

- [C57] T. Chou, W. Tang, J. Botimer, and Z. Zhang, “CASCADE: Connecting RRAMs to extend analog dataflow in an end-to-end in-memory processing paradigm,” in
*IEEE/ACM Int. Symp. Microarchitecture*(*MICRO*), Columbus, OH, Oct. 2019, pp. 114-125. - [C56] J.-F. Zhang, C.-E. Lee, C. Liu, Y. S. Shao, S. W. Keckler, and Z. Zhang, “SNAP: A 1.67 – 21.55TOPS/W sparse neural acceleration processor for unstructured sparse deep neural network inference in 16nm CMOS,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2019, pp. 306-307. - [C55] Y. Tao, S.-G. Cho, and Z. Zhang, “A 3.25Gb/s, 13.2pJ/b, 0.64mm2 configurable successive-cancellation list polar decoder using split-tree architecture in 40nm CMOS,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2019, pp. 240-241. - [C54] T. Chen, J. Botimer, T. Chou, and Z. Zhang, “An SRAM-based accelerator for solving partial differential equations,” in
*IEEE Custom Integrated Circuits Conf.*(*CICC*), Austin, TX, Apr. 2019. - [C53] S.-G. Cho, E. Beigné, and Z. Zhang, “A 2048-neuron spiking neural network accelerator with neuro-inspired pruning and asynchronous network on chip in 40nm CMOS,” in
*IEEE Custom Integrated Circuits Conf.*(*CICC*), Austin, TX, Apr. 2019. - [C52] C. Liu and Z. Zhang, “Inference and learning hardware architecture for neuro-inspired sparse coding Algorithm,” in
*IEEE Biomedical Circuits Syst. Conf.*(*BioCAS*), Cleveland, OH, Oct. 2018. (Invited) - [C51] H.-S. Wu, Z. Zhang, and M. Papaefthymiou, “A 0.23mW heterogeneous deep-learning processor supporting dynamic execution of conditional neural networks,” in
*European Solid-State Circuits Conf.*(*ESSCIRC*), Dresden, Germany, Sep. 2018. - [C50] S. Song, W. Tang, T. Chen, and Z. Zhang, “LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS,” in
*IEEE Custom Integrated Circuits Conf.*(*CICC*), San Diego, CA, Apr. 2018. - [C49] C.-E. Lee, Y. S. Shao, J.-F. Zhang, A. Parashar, J. Emer, S. W. Keckler, and Z. Zhang, “Stitch-X: An accelerator architecture for exploiting unstructured sparsity in deep neural networks,” in
*SysML Conf.*, Stanford, CA, Feb. 2018. - [C48] W. Tang, H. Prabhu, L. Liu, V. Öwall, and Z. Zhang, “A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2018, pp. 224-225. - [C47] S. Sun, S.-G. Cho, and Z. Zhang, “Post-processing methods for improving coding gain in belief propagation decoding of polar codes,” in
*IEEE Global Commun. Conf.*(*GLOBECOM*), Singapore, Dec. 2017. - [C46] C. Liu, S.-G. Cho, and Z. Zhang, “A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS,” in
*IEEE Asian Solid-State Circuits Conf.*(*A-SSCC*), Seoul, Korea, Nov. 2017, pp. 233-236. - [C45] S. Lu, Z. Zhang, and M. Papaefthymiou, “A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices,” in
*IEEE Asian Solid-State Circuits Conf.*(*A-SSCC*), Seoul, Korea, Nov. 2017, pp. 65-68. - [C44] J. K. Kim, P. Knag, T. Chen, C. Liu, C.-E. Lee, and Z. Zhang, “High-performance spiking neural net accelerators for embedded computer vision applications,” in
*IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf.*(*S3S*), San Francisco, CA, Oct. 2017. (Invited) - [C43] C.-E. Lee, T. Chen, and Z. Zhang, “A 127mW 1.63TOPS sparse spatio-temporal cognitive SoC for action classification and motion tracking in videos,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2017, pp. 226-227. - [C42] F. N. Buhler, P. Brown, J. Li, T. Chen, Z. Zhang, and M. P. Flynn, “A 3.43TOPS/W 48.9pJ/pixel 50.1nJ/classification 512 analog neuron sparse coding neural network with on-chip learning and classification in 40nm CMOS,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2017, pp. 30-31. - [C41] H.-S. Wu, Z. Zhang, and M. C. Papaefthymiou, “A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2017, pp. 348-349. - [C40] Z. Li, Q. Dong, M. Saligane, B. Kempke, S. Yang, Z. Zhang, R. Dreslinski, D. Sylvester, D. Blaauw, and H. S. Kim, “A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2017, pp. 62-63. - [C39] S. Lu, Z. Zhang, and M. Papaefthymiou, “A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh,” in
*IEEE Asian Solid-State Circuits Conf.*(*A-SSCC*), Toyama, Japan, Nov. 2016, pp. 133-136. - [C38] S. Sun, S.-G. Cho, and Z. Zhang, “Error patterns in belief propagation decoding of polar codes and their mitigation methods,” in
*Asilomar Conf. Signals, Syst., Comput.*, Pacific Grove, CA, Nov. 2016. (Invited) - [C37] T. Gaier, P. Kangaslahti, B. Lambrigtsen, I. Ramos-Perez, A. Tanner, D. McKague, C. Ruf, M. Flynn, Z. Zhang, R. Backhus, and D. Austerberry, “A 180 GHz prototype for a geostationary microwave imager/sounder-GEOSTAR-III,” in
*IEEE Int. Geosci. Remote Sens. Symp.*(*IGARSS*), Beijing, China, Jul. 2016, pp. 2021-2023. - [C36] W. Tang, C.-H. Chen, and Z. Zhang, “A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2016. - [C35] P. Knag, C. Liu, and Z. Zhang, “A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2016. - [C34] S. Sun and Z. Zhang, “Architecture and optimization of high-throughput belief propagation decoding of polar codes,” in
*IEEE Int. Symp. Circuits Syst.*(*ISCAS*), Montreal, Canada, May 2016, pp. 165-168. (Invited) - [C33] T.-C. Ou, Z. Zhang, and M. Papaefthymiou, “A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors,” in
*IEEE Asian Solid-State Circuits Conf.*(*A-SSCC*), Xiamen, China, Nov. 2015. - [C32] S. Lu, Z. Zhang, and M. Papaefthymiou, “1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2015, pp. 246-247. - [C31] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, “A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2015, pp. 50-51. - [C30] C.-H. Chen, W. Tang, and Z. Zhang, “A 2.4mm2 130mW MMSE-nonbinary LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2015, pp. 338-339. - [C29] F. Sheikh, C.-H. Chen, D. Yoon, B. Alexandrov, K. Bowman, A. Chun, H. Alavi, and Z. Zhang, “3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication,” in
*IEEE Workshop Signal Process. Syst.*(*SIPS*), Belfast, UK, Oct. 2014. - [C28] Y. S. Park, Y. Tao, S. Sun, and Z. Zhang, “A 4.68Gb/s belief propagation polar decoder with bit-splitting register file,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2014, pp. 117-118. - [C27] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, “A 6.67mW sparse coding ASIC enabling on-chip learning and inference,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2014, pp. 61-62. - [C26] S. Gaba, P. Knag, Z. Zhang, and W. Lu, “Memristive devices for stochastic computing,” in
*IEEE Int. Symp. Circuits Syst.*(*ISCAS*), Melbourne, Australia, Jun. 2014, pp. 2592-2595. (Invited) - [C25] T.-C. Ou, Z. Zhang, and. M. C. Papaefthymiou, “An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2014, pp. 462-463. - [C24] D. Jeon, Y.-P. Chen, Y. Lee, Y. Kim, Z. Foo, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, “An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2014, pp. 416-417. - [C23] C.-H. Chen, K. Bowman, C. Augustine, Z. Zhang, and J. Tschanz, “Minimum supply voltage for sequential logic circuits in a 22nm technology,” in
*IEEE Int. Symp. Low Power Electron. Des.*(*ISLPED*), Beijing, China, Sep. 2013, pp. 181-186. - [C22] D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, “A low-power VGA full-frame feature extraction processor,” in
*IEEE Int. Conf. Acoust., Speech, Signal Process.*(*ICASSP*), Vancouver, Canada, May 2013, pp. 2726-2730. - [C21] C.-H. Chen, Y. Tao, and Z. Zhang, “Efficient in situ error detection enabling diverse path coverage,” in
*IEEE Int. Symp. Circuits Syst.*(*ISCAS*), Beijing, China, May 2013, pp. 773-776. (**Best Student Paper Award Finalist**) - [C20] Y. S. Park, Y. Tao, and Z. Zhang, “A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2013, pp. 422-423. - [C19] D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, “A 470mV 2.7mW feature extraction accelerator for micro-autonomous vehicle navigation in 28nm CMOS,” in
*IEEE Int. Solid-State Circuits Conf.*(*ISSCC*), San Francisco, CA, Feb. 2013, pp. 166-167. - [C18] J. K. Kim, J. A. Fessler, and Z. Zhang, “Perburbation-based error analysis of iterative image reconstruction algorithm for X-ray computed tomography,” in
*Int. Conf. Image Formation in X-Ray Computed Tomography*, Salt Lake City, UT, Jun. 2012, pp. 194-197. - [C17] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, “A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM,” in
*Symp. VLSI Circuits*, Honolulu, HI, Jun. 2012, pp. 114-115. - [C16] Y. Tao, Y. S. Park, and Z. Zhang, “High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders,” in
*IEEE Int. Symp. Circuits Syst.*(*ISCAS*), Seoul, Korea, May 2012, pp. 2625-2628. - [C15] H. Li, Y. S. Park, and Z. Zhang, “Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation,” in
*ACM Int. Symp. Field-Programmable Gate Arrays*(*FPGA*), Monterey, CA, Feb. 2012, pp. 167-170. - [C14] J. Wang, L. Dolecek, Z. Zhang, and R. Wesel, “Absorbing set spectrum approach for practical code design,” in
*IEEE Int. Symp. Inf. Theory*(*ISIT*), Saint Petersburg, Russia, Aug. 2011, pp. 2726-2730. - [C13] J. K. Kim, Z. Zhang, and J. A. Fessler, “Hardware acceleration of iterative image reconstruction for X-ray computed tomography,” in
*IEEE Int. Conf. Acoust., Speech, Signal Process.*(*ICASSP*), Prague, Czech Republic, May 2011, pp. 1697-1700. - [C12] M. Weiner, B. Nikolic, and Z. Zhang, “LDPC decoder architecture for high-data rate personal-area networks,” in
*IEEE Int. Symp. Circuits Syst.*(*ISCAS*), Rio de Janeiro, Brazil, May 2011, pp. 1784-1787. (Invited) - [C11] C.-H. Chen, Y. Kim, Z. Zhang, D. Blaauw, D. Sylvester, H. Naeimi, and S. Sandhu, “A confidence-driven model for error-resilient computing,” in
*Design, Autom. Test in Europe Conf.*(*DATE*), Grenoble, France, Mar. 2011. - [C10] L. Dolecek, J. Wang, and Z. Zhang, “Towards improved LDPC code designs using absorbing set spectrum properties,” in
*Int. Symp. Turbo Codes Iterative Inform. Process.*(*ISTC*), Brest, France, Sep. 2010, pp. 477-481.

**Conference Proceedings (Prior to 2010)**

- [C9] Z. Zhang, L. Dolecek, P. Lee, V. Anantharam, M. J. Wainwright, B. Richards, and B. Nikolic, “Low error rate LDPC decoders,” in
*Asilomar Conf. Signals, Syst., Comput*., Pacific Grove, CA, Nov. 2009, pp. 1278-1282. (Invited) - [C8] Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, “A 47 Gb/s LDPC decoder with improved low error rate performance,” in
*Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2009, pp. 286-287. (**Best Student Paper Award**) - [C7] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, “Lowering LDPC error floors by postprocessing,” in
*IEEE Global Commun. Conf.*(*GLOBECOM*), New Orleans, LA, Nov. 2008. - [C6] P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolic, and M. Wainwright, “Error floors in LDPC codes: fast simulation, bounds and hardware emulation,” in
*IEEE Int. Symp. Inf. Theory*(*ISIT*), Toronto, Canada, Jul. 2008, pp. 444-448. - [C5] Z. Zhang, R. Winoto, A. Bahai, and B. Nikolic, “Peak-to-average power ratio reduction in an FDM broadcast system,” in
*IEEE Workshop Signal Process. Syst.*(*SIPS*), Shanghai, China, Oct. 2007, pp. 25-30. - [C4] L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, and B. Nikolic, “Evaluation of the low frame error rate performance of LDPC codes using importance sampling,” in
*IEEE Inf. Theory Workshop*(*ITW*), Tahoe City, CA, Sep. 2007, pp. 202-207. - [C3] L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, “Analysis of absorbing sets for array-based LDPC codes,” in
*IEEE Int. Conf. Commun.*(*ICC*), Glasgow, UK, Jun. 2007, pp. 6261-6268. - [C2] Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic, “Quantization effects in low-density parity-check decoders,” in
*IEEE Int. Conf. Commun.*(*ICC*), Glasgow, UK, Jun. 2007, pp. 6231-6237. - [C1] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. Wainwright, “Investigation of error floors of structured low-density parity-check codes by hardware emulation,” in
*IEEE Global Commun. Conf.*(*GLOBECOM*), San Francisco, CA, Nov. 2006. (**Best Student Paper Award Finalist**)

**Book Chapters**

- [B3] P. Knag, S. Gaba, W. Lu and Z. Zhang, “RRAM solutions for stochastic computing,” in
*Stochastic Computing: Techniques and Applications*, W. Gross and V. C. Gaudet, Eds. Springer, 2019. - [B2] S. Sun and Z. Zhang, “Design of high-performance error-correcting codes using FPGA,” in
*Reconfigurable Logic: Architecture, Tools and Applications*, P.-E. Gaillardon, Ed. Boca Raton, FL: CRC Press, 2015. - [B1] C.-H. Chen, P. Knag, and Z. Zhang, “Soft error resilient circuit design,” in
*VLSI: Circuits for Emerging Applications*, T. Wojcicki, Ed. Boca Raton, FL: CRC Press, 2014.

**Technical Reports**

- [T2] Z. Zhang, “Design of LDPC decoders for improved low error rate performance,” Ph.D. dissertation, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 2009.
- [T1] Q. Zhu, Z. Zhang, A. Pinto, and A. L. Sangiovanni-Vincentelli, “On-chip networks modeling and simulation,” Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Technical Report EECS-2006-126, Oct. 2006.